Sundance SMT326v2 - Manual (Page 24)

Release Page 24 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
How To DMA
To relieve the ‘C44 of any unnecessary burden of waiting for a new sample to be acquired, it is
possible (if a little complicated) to request that the ‘C44’s DMA controller perform the entire transfer
of samples into memory (or comm port) with only a single interrupt on completion.
The procedure would be to setup a series of 4 DMA operation (DMAOP) each one linking to the
following one, with DMA operation 4 linking to DMA operation 1.
DMAOP1 would synchronise to the FPGA interrupt IIOF0, have a source address pointing to
0x80200000 (FPGA source), destination address pointing to the required memory address (BUF), a
transfer length of 1, and a link pointer pointing to DMAOP2.
DMAOP2 would have no synchronisation, have a source address pointing to 0x80200001, destination
address of BUF+1, a transfer length of 15, and a link pointer pointing to DMAOP3.
DMAOP3 would synchronise to the FPGA interrupt IIOF0, have a source address pointing to
0x80200010 (FPGA source), destination address pointing to the required memory address (BUF+16),
a transfer length of 1, and a link pointer pointing to DMAOP4.
DMAOP4 would have no synchronisation, have a source address pointing to 0x80200011, destination
address of BUF+17, a transfer length of 15, a link pointer pointing to DMAOP1, and would set the
TCC bit (to enable an interrupt on completion).
In operation, the FPGA will generate an interrupt on IIOF0 for the left channel say, this will trigger
DMAOP1 to read and store the first channel. DMAOP2 will then start and read and store the next 15
channels. DMAOP3 is then started, which will wait for the next interrupt on IIOF0 (the right channels).
When this is received, DMAOP3 will read and store channel 16 and then start DMAOP4. DMAOP4
reads and stores the remaining 15 channels, generates an interrupt to the ‘C44 and reloads
DMAOP1.
When the ‘C44 receives its interrupt, the whole 32 channels will be stored at BUF.
Various simpler alternatives are available, including the ‘C44 responding to the left and right channel
interrupts, and performing the transfers itself.