Sundance SMT326v2 - Manual (Page 6)

Release Page 6 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Global Bus Resource
The global bus has access to SRAM, DACs, ADCs, LED control register and ADC control registers.
Global SRAM
The SRAM is composed using a 72 pin ZIP SRAM module. Up to 4Mbytes are available with
the largest module. Faster SRAM (15ns) would be needed for 60MHz operation.
The global SRAM is accessed at address 0x80000000 on processor strobe STRB0.
CODEC
Sixteen stereo audio CODEC devices are employed on the SMT326 to provide 32 channels
of analog input and 32 channels of analog output.
The CODECs have a serial output and are interfaced to the ‘C44 global bus via an XC4006
FPGA. Configuration of the CODECs is performed through an I
2
C serial interface. The
CODEC can respond to two I
2
C addresses, primary and alternate. Eight of the CODECs
respond to their primary address, and the other eight to their secondary address. Pairs of
CODECs are then selected within the LED Control register.
DAC
The DAC output signals range from -2.83V to +2.83V (2Vrms) and are available on
the miniature co-ax connectors along the top and bottom edges.
The DAC outputs are subject to a digital filter which limits the bandwidth (0.1dB) to
10 - 20kHz, and is DC coupled.
The differential output of the CODEC is buffered with an op-amp which provides a
single-ended output.
ADC
The ADC input signal range is AC coupled (1Vrms). These signals are presented to
the ADC circuitry through connectors mounted on the top and bottom edges of the
board.
A single-ended analog input is buffered to produce the differential input required by
the codec.