Sundance SMT326v2 - Manual (Page 7)

Release Page 7 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
CODEC Clocking
The CODEC clock is generated by an on-board oscillator. There is no way to change
via software the sampling rate.
The on-board oscillator can be exchanged for any oscillator which is packaged in an
8-pin DIP. The oscillator frequency is chosen such that;-
fosc=m x fsamp < 30MHz
where fosc is the oscillator frequency,
m = oversample rate / 2 = (1024), and
fsamp is the sample rate.
i.e.:
if fosc=50MHz then fsamp=50 Ksamples/sec
CODEC Control
CODEC Start
After power-on or reset, the CODECs will be held in a reset state (not
sampling). To start the CODECs sampling a processor write to address
0x80200020 with D7 set, using processor strobe STRB1, must be performed.
This is a global signal and all CODECs will start at the same time (within one
CODEC input clock period).
CODEC Stop
To stop acquisition a processor write to address 0x80200020 with D7 clear,
using processor strobe STRB1, must be performed. This is a global signal
and all CODECs will stop at the same time. Note that the only advantage of
stopping the CODECs is to reduce power consumption. An alternative to
stopping sampling is to disable the interrupt enable within the ‘C44.
CODEC Interrupt & Status
The CODECs operate in a left/right mode. Although all channels are
sampled at the same point, the serial data from the CODECs are transmitted
in two phases as 16 channels of left followed by 16 channels of right. At the
end of each of these phases an interrupt is signalled on IIOF0. The first
interrupt received after removing reset is from the left channel.
The interrupt must be set to edge triggered as it only remains active for
approximately 120ns (hence it cannot be polled reliably by the ‘C44 within
the IIF register).
When the address 0x80200020 is read, the codec interface status is
returned. Bit 0 reflects the IIOF0 state, and bit 1 indicates which phase (left
or right) is able to be accessed by the ‘C44. When bit 1 is 0, then the ‘C44
can access the first 16 channels (left).