Sundance SMT326v2 - Manual (Page 5)

Release Page 5 of 24 SMT326 DSP PC/ISA System User Guide
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Local Bus Resource
The local bus has access to a bank of SRAM and the ID ROM.
Local SRAM
The SRAM is composed using a 72 pin ZIP SRAM module. Up to 4Mbytes are available with
the largest module. Faster SRAM (15ns) would be needed for 60MHz operation.
The local SRAM is accessed at address 0x00300000 on processor strobe LSTRB0.
ID ROM
On the local bus of the 'C44 is an ID ROM which contains module specific data to enable
operating systems such as 3L to determine the processor network architecture.
This device is a 32k byte erasable ROM, and can be re-written by the 'C44. It must be
accessed with 7 wait states at address 0x70000000 on processor strobe LSTRB0.
For write protection purposes, in addition to a software mechanism, a jumper, JP4, must be
inserted to enable writes to the ID ROM.
For storage of TIM compliant ID information, this ROM appears as a 4 bit ID ROM.
This device also contains the configuration code for the Xilinx Codec Interface.
Local Memory Interface Control Register (LMICR)
Within the 'C44 is a register which determines how the bus is partitioned and how many wait
states to use for accesses. There are two values which must be programmed here. One is for
ID ROM access, and the other for SRAM access.
For ID ROM access the value 0x3E39FF50 must be programmed into the LMICR.
For SRAM access (normal operation) the value 0x3EF78050 must be programmed into the
LMICR. When using an operating system like 3L, the loading of this register is performed
using the value within the ID ROM.