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Preferred master switch – Sierra Video Yosemite User Manual

Page 73

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505150 PROCESSORS

67

Preferred Master Switch

A requirement of the two processors is to set one CPU as the master processor and the other CPU as the
slave. The setting is made with DIP Switch S1-1. It is essential that S1-1 be set opposite on the two
processors for redundancy to function properly. This DIP Switch setting determines which processor will
become the master processor when both processors are powered on at the same time. Furthermore, it is
recommended that the processor in the uppermost or leftmost slot be the master with S1-1 turned ON,
and the processor in the lower-right most slot be the slave with S1-1 turned OFF. It will make it easier for
you to troubleshoot and verify DIP switch settings with the health monitoring LEDs. See DIP Switch
settings and above picture. If S1-1 is set to the same setting on both processors, the router will not
function properly.

Position of Redundant Processors

Processor Slot

Recommended S1-1 Setting

Top or Left

ON

Bottom or Right

OFF

Note:

IF S1-1 is set to the same setting on both processors, the routing switcher will not function properly.

It is important to know that the setting of S1-1 only determines the processors as master and standby
immediately following power-up. Down the road, the standby processor may take over as master
processor, in which case the setting of S1-1 will no longer indicate the correct master processor. Always
use LEDa to determine which processor is actually the master, not the S1-1 DIP Switch setting.

The current master processor turns on its LEDa, and the standby processor turns LEDa off. Thus, only
one of the two LEDa indicators should be lit at any one time. However, in the unlikely event that the
processor dies, the processor may be unable to turn its LEDa off. Both LEDa monitors would be
illuminated indicating the standby processor has relieved the master processor due to failure. Always look
for the processor with LEDa on first, and know that it is the current master processor in control of the
routing switcher.