Figures, Tables – Sensoray 626 User Manual
Page 4
Sensoray Model 626 Instruction Manual
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2
10.7 T
RIGGERING
A C
OUNTER
L
OAD
............................................................................................................................... 21
10.8 C
LEARING
C
OUNTER
B F
ROM
C
OUNTER
A’
S
O
VERFLOW
........................................................................................ 21
10.9 L
ATCHING
T
HE
C
OUNTERS
....................................................................................................................................... 21
10.10 I
NTERRUPTS
............................................................................................................................................................. 22
10.10.1 Interrupts
While Under Battery Backup ......................................................................................................... 22
10.10.2 Interrupt
source Selection............................................................................................................................... 22
10.10.3 Clearing An interrupt...................................................................................................................................... 22
10.10.4 Counter
Interrupt Handling............................................................................................................................ 22
11. W
ATCHDOG
/M
ISCELLANEOUS
R
EGISTERS
............................................................................................................... 23
11.1 B
ATTERY
C
HARGING
................................................................................................................................................ 23
11.2 W
ATCHDOG
O
SCILLATOR
......................................................................................................................................... 24
11.2.1 Overview ......................................................................................................................................................... 24
11.2.2
Testing the Watchdog Without Resetting the Host.......................................................................................... 24
11.2.3 Watchdog
Enable & Period Selection ............................................................................................................ 24
11.2.4 Clearing the Watchdog ................................................................................................................................... 24
11.2.5 Watchdog LED Status..................................................................................................................................... 24
11.3 D
IGITAL
O
UTPUTS
1-6 S
OURCE
S
ELECTION
............................................................................................................. 25
12. BATTERY
BACKUP ................................................................................................................................................ 25
13. ANALOG
INPUTS .................................................................................................................................................... 26
14. ANALOG
OUTPUTS ................................................................................................................................................ 26
APPENDIX A: SPECIFICATIONS ...................................................................................................................................... 27
APPENDIX B: DIGITAL I/O CONNECTORS ................................................................................................................... 28
APPENDIX C: ENCODER CONNECTORS ....................................................................................................................... 29
APPENDIX D: A/D AND D/A CONNECTORS................................................................................................................... 30
FIGURES
Figure 1 System Block Diagram .................................................................................................................6
Figure 2 Board Layout.................................................................................................................................7
Figure 3 Digital I/O Channels .....................................................................................................................9
Figure 4 Differential pair encoder. ............................................................................................................16
Figure 5 Single ended encoder. (TTL or CMOS)......................................................................................16
Figure 6 Single ended event counter with external count direction & index control...............................16
Figure 7 Block diagram of a counter pair..................................................................................................17
TABLES
Table 1 MISC1 & MISC2 Registers Initial States..................................................................................8
Table 2 Digital I/O Initial States ..............................................................................................................8
Table 3 Counter Initial States ..................................................................................................................8
Table 4 Digital I/O Register Offsets.........................................................................................................9
Table 5 Writing to Digital Outputs........................................................................................................10
Table 6 Reading Digital Inputs ..............................................................................................................10
Table 7 Selecting Positive or Negative Edge Capture ..........................................................................11
Table 8 Enabling & Disabling Edge Capture .......................................................................................11
Table 9 Reading Captured Edges ..........................................................................................................12
Table 10 Reading the Status of the Interrupt Enable Registers .........................................................12