Sensoray 626 - Manual (Page 26)

Sensoray Model 626 Instruction Manual 24
11.2 Watchdog Oscillator
11.2.1 Overview
Embedded systems often include a watchdog timer to regain program control following an unplanned
loss of control by the PCI bus master. In such systems, the CPU is responsible for periodically clearing
the watchdog timer. Should the CPU crash, the watchdog won't be cleared and will eventually overflow
and cause the CPU to be reset through the PCI bus.
After a reset the watchdog timer is disabled and the watchdog oscillator selection is cleared.
To use the watchdog, it needs to be enabled and the watchdog period needs to be set.
Any external hardware also may be reset by the watchdog timer with the additional relay. This relay has
one switched contact group insulated from internal circuit.
11.2.2 Testing the Watchdog Without Resetting the Host
Under normal conditions a watchdog time-out will cause the PCI bus to be reset. By removing jumper
JP1 no PCI reset will occur although the watchdog will be fully functional internally. This may be useful
during development as the status of the watchdog can be obtained from bit 14 of Misc1. A ‘1’ means it
has timed out. The watchdog output at JP1 is an ‘open collector’ output.
The relay watchdog output may be disabled by removing jumper J10.
11.2.3 Watchdog Enable & Period Selection
Bits 1 & 0 of MISC2 (92 hex) are used to select a period of 1 /
8
, 1 /
2
, 1 or 10 seconds while bit 2 is used to
enable the watchdog. (See “Table 21 Write to MISC2 90 (hex)” P23).
Before writing to any of the bits of MISC2, except bit 15 (Clear watchdog), the write enable (bit 15) of
MISC1 must be set. This is to prevent accidental modification of the watchdog settings by a crashed
CPU. It is a good idea to clear this bit immediately after writing to MISC2.
Although the Enable and period selection bits are in the same register, first the register must be written
to with the ‘Watchdog Enable’ bit = ‘1’ (bit 2) and then the register must be written to again with bit 2
again = ‘1’ and the period selection bits set as desired. This is because the period selection bits are held
in a cleared state (
1 /
8
th of a second) and cannot be changed until the ‘Watchdog enable’ bit is = ‘1’.
11.2.4 Clearing the Watchdog
To prevent a PCI reset the watchdog timer must be cleared at least once within the period of the
watchdog timer. To do this bit 15 (“Write Enable”) of MISC1 (88 hex) must first be cleared and then bit
15 (Clear watchdog) of MISC2 (92 hex) must be set. The clear watchdog bit is automatically cleared
after the watchdog has been cleared.
11.2.5 Watchdog LED Status
If the watchdog is disabled the red LED will be off continuously.
When the watchdog is enabled the LED will be off for ½ the selected watchdog period, then on for ½
the period and then the watchdog will reset the PCI bus (Pulled low) if JP1 is inserted or if the jumper is
not inserted then bit 14 of Misc2 will go high and the LED will flash at ½ the selected watchdog period.