Sensoray 626 - Manual (Page 15)

Sensoray Model 626 Instruction Manual 13
9.5.4 Reading the Status of the Capture Enable Register
Table 12 Reading the Status of the Capture Enable Registers
Offset Input Channel Number
(Hex)
Register
Name
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
4E RDCAPSELA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5E RDCAPSELB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
6E RDCAPSELC 47
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RDCAPSELA, B & C are used to determine which, if any, channels have edge capturing enabled. A ‘1’
shows that the corresponding channel has edge capturing enabled.
9.5.5 Clearing a Captured Edge
Once an edge has been captured it can be cleared by disabling it in its WRCAPSEL register. Doing this
will also clear any accompanying interrupt. Obviously it will need to be re-enabled if another edge is to
be captured.
9.6 Digital Input Interrupts
9.6.1 Selecting Interrupt on Edge Capture
Table 13 Selecting Interrupt on Edge Capture
Offset Input Channel Number
(Hex)
Register
Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
42 WRINTSELA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
52 WRINTSELB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
62 WRINTSELC 47
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Write to the correct WRINTSEL register with a ‘1’ to enable and ‘0’ to disable interrupts on that
channel. An interrupt will only occur if the channel has been enabled using one of the WRCAPSEL
registers & the WREDCAP register. The interrupts do not have to be enabled to capture an edge, an
edge can still be captured but the RDCAPFLG registers will have to be polled to see if an edge capture
has occurred.
9.6.2 Digital Input Interrupt Handling
There is only one main interrupt to the system from the 626. Once this interrupt has been received it is
up to the user to determine whether it originated from the counters (See “Counter Interrupt Handling”
P22) or the digital inputs.
The RDCAPFLG registers and the corresponding RDINTREG registers need to be logically ‘anded’
together to determine if an interrupt has occurred on a particular digital input channel.
An interrupt must be cleared once it has been handled to prevent it from causing multiple interrupts.