Sensoray 626 - Manual (Page 17)

Sensoray Model 626 Instruction Manual 15
10.1.3 Interrupts
Each counter can generate an interrupt on overflow, index or both.
10.1.4 Overflow Outputs
The overflow output of each counter can be individually connected to a digital output. When the counter
overflows a single pulse will occur pulling the output load low for 2 clock cycles (500nsec).
10.1.5 Index Inputs
Each counter has a hardware or software controlled index input that can programmed to perform clear,
pre-load or latch functions.
10.1.6 Counter Inputs
Each counter has various input modes including:
• Quadrature encoders with hardware or software controlled index.
• Single ended event & direction & index inputs.
• System clock with hardware or software control of direction & index for event timing.
Each counter channel has two clock input phases (referred to as channels in this manual) named “A” and
“B”. Depending on the application, one or both of these signals may be connected to an encoder or to a
pulse source.
If both phases are used, they are assumed to be quadrature encoded, meaning that they are 90 degrees
out of phase. In this case, counters will count both up and down based on the timing relationship of the
two-phase inputs.
If only one phase is used, the input is said to be single-phase. In this case, counter channels will count
either up or down for each pulse on the phase input depending on the polarity of the direction input. This
configuration is typically used to count pulses from devices that produce a single clock output.
Quadrature encoders for positioning systems have advantages over single-phase encoders. Counters will
not accumulate errors when an encoder changes direction or dithers about a state transition boundary.
Also, it is possible to increase encoder resolution by clocking the counters at a multiple of the single-
phase clock rate.
10.1.7 Power failure
If an external NiCad battery is connected and fully charged and the Battery Enable bit of MISC2 is set,
then if power is lost, all the counter registers will be held and the counters will continue to operate even
though the rest of the system is down.
Note the counter interrupts are disabled when the system powers up but if an interrupt occurred during
power down then it will occur the moment the interrupts are re-enabled.