Measurement Computing PC104-DAS08 - Manual (Page 18)

counter 1 would then be wired to the interrupt input (pin 10). The slowest rate
would then be once every 17 minutes.
3.8 DIGITAL INPUT
The digital inputs are TTL-level lines. They feed an 8-bit register which has other
on-board signals applied to it. The resultant 8-bit status byte can be read at BASE
address + 2.
The digital inputs IP1, IP2 & IP3 can be used as status lines to trigger or hold off
A/D conversions, and in fact, the Universal Library uses IP1 for that purpose.
3.9 DIGITAL OUTPUT
The digital output lines, OP1, OP2, OP3 & OP4 are TTL level lines which are
controlled with part of an 8-bit register located at BASE address + 2. These lines
may be used to control the multiplexer address on an external CIO-EXP32
differential amplifier/ multiplexer if one is installed.
3.10 TRIGGER & INTERRUPT LOGIC
The trigger logic works as follows: The INTERRUPT REQ signal on Pin 10 of the
40-pin connector is an input to a flip-flop. It can be read at BASE address + 2 on the
IRQ bit. The PC104-DAS08 can be triggered by polling this bit until a trigger pulse
(rising edge) has occurred. It must be reset by a write to BASE + 2 before it can
respond to additional rising edges.
By writing a 1 to the INTE control bit at BASE + 2, the rising edge detected by the
flip-flop will be translated into an interrupt pulse which can be used to interrupt the
CPU's 8259 interrupt controller on the PC motherboard.
The interrupt level jumper on the PC104-DAS08 must also be installed. Move it
from the 'X' position to the IRQ number you want the interrupt pulse on.
The 82C54 counter/timer chip is primarily a pacer for A/D samples. It is an integral
part of the trigger logic. To employ the 82C54 as an A/D pacer, wire the output of
the counter you program to provide pacing pulses directly into the INTERRUPT
REQ input (pin 10).
14