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4 known designflow issues, 1 general quartus issues, 1 qsys: avalon read error – BECKHOFF EtherCAT IPCore Section III User Manual

Page 8: 2 quartus 14, Known designflow issues, General quartus issues, Qsys: avalon read error, Quartus 14

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EtherCAT IP Core for Altera FPGAs

Slave Controller

– EtherCAT IP Core Data Sheet Addendum

5

2.4

Known Designflow Issues

2.4.1

General Quartus issues

2.4.1.1

Qsys: Avalon read error

With Qsys, a 32 bit read access to the EtherCAT IP Core might have gaps between the bytes. The prefetch feature (Data width of smallest Avalon Master is set to 2 or 4 byte), which is available in EtherCAT IP Core versions before
V3.0.0, does not support these gaps, read errors occur as a consequence.

Solution
Set the configuration option Data width of smallest Avalon Master to 1 byte, prefetch is disabled then.

2.4.2

Quartus 14

2.4.2.1

Quartus 14.1 Arria 10: Tristate drivers are not properly connected

With Quartus 14.1 and Arria 10 devices, tristate drivers may not be properly connected (IN and OE pins are swapped during technology mapping). This issue does not depend on internal/external tristate drivers.

Warning message:

Warning (12620): Input port OE of I/O output buffer "PROM_DATA~output" is not connected, but the atom is driving a bi-directional pin

The warning message cannot be ignored since the tristate driver is actually not properly connected. This issue is already approved by Altera.

Solution
None.

2.4.2.2

Quartus 14.0 and later: Cyclone III example designs are not synthesizable

Cyclone III devices are not supported anymore by Quartus 14, corresponding example designs cannot be synthesized

Solution
None. Use previous Quartus versions.

2.4.2.3

Quartus 14.0 with EtherCAT IP Core V3.0.0-V3.0.6: DE2-115 example designs are not working

The DE2-115 example designs are not working when synthesized using Quartus 14.0 (no communication, no display). The reason is that the PLL remains in reset state, because the areset input pin is not connected. Quartus 14.0 seems
to use a different input value for this signal, causing the reset to be active all the time.

Solution
Open Qsys, export the altpll_0 module’s areset_conduit signal, and connect it to GND. The warning regarding this conduit disappears.