BECKHOFF EtherCAT IPCore Section III - Manual (Page 13)

EtherCAT IP Core for Xilinx FPGAs
Slave Controller – EtherCAT IP Core Data Sheet Addendum 10
3.3.3 Vivado 2014
3.3.3.1 Vivado 2014.4: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK
Vivado 2014.4 generates a wrong hardware description file if the EtherCAT IP core (and probably any other AXI slave) is connected externally to the Zynq block design. This causes the SDK to fail in generating the example software with
such an error message:
[Hsi 55-1464] Hardware instance __EMPTY__ not found in the design
This issue is partially fixed in Vivado 2015.1. A similar answer record (AR63036) can be found on the Xilinx website.
Solution
Please use Vivado 2015.1 (and newer) or 2014.3 to implement this example design and other designs which have the EtherCAT IP Core connected externally to the Zynq block design.
3.3.3.2 Vivado 2014.3: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Vivado 2014.3 may stop during Technology Mapping with an access violation occasionally. Just repeat the synthesis run again and again until it succeeds (1-6 iterations until success have been seen). This issue is already approved by
Xilinx and should be fixed in 2014.3 Update 1.
The Vivado console stops with these messages:
[...]
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check '.runs/synth_1/hs_err_pid6336.log' for details
The mentioned log file contains no further details except for the dump file:
#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_.dmp instead.
Solution
Run the synthesis again several times until it succeeds or update Vivado.
3.3.3.3 Vivado until 2014.3: Tri-state buffers inside EtherCAT IP Core
If the EtherCAT IP Core is configured to have internal tri-state buffers (e.g. for EEPROM/MI), Vivado 2014.2 (and maybe others) does not correctly implement the tristate drivers. Instead of a tristate output, a push-pull output is
implemented, which might not even toggle. This issue is approved by Xilinx, it should be solved in 2014.3.
Solution
Execute the following Tcl command in the Vivado GUI Tcl Console:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter enableTristateBubbleUp 1"
3.3.3.4 Vivado until 2014.2: The resource consumption of the EtherCAT IP Core is too high
The resource consumption of the EtherCAT IP Core is about 30% higher when it is synthesized with Vivado instead of ISE. This issue is approved by Xilinx, it is targeted to be solved in 2014.3.
Solution
Refer to Answer Record 61518 for a Vivado 2014.2 patch (this is not publicly available on the website). After applying the patch, the resource consumption is still higher, but much more acceptable.