BECKHOFF EtherCAT IPCore Section III - Manual (Page 11)

EtherCAT IP Core for Xilinx FPGAs
Slave Controller – EtherCAT IP Core Data Sheet Addendum 8
3.3 Known Designflow Issues
3.3.1 General Vivado issues
3.3.1.1 Vivado Upgrade IP: Warning on port differences
When upgrading the ZC702_AXI_VIVADO example design to a newer Vivado version, a warning may be issued regarding port differences:
[IP_Flow 19-3298] Detected external port differences while upgrading IP 'ZYNC_BLOCK_processing_system7_0_0'. These changes may impact your design.
These warnings can be ignored since the different port signals are not used by the example design.
3.3.1.2 The resource consumption of the EtherCAT IP Core is too high
The EtherCAT IP Core has a higher resource consumption when used with Vivado instead of ISE.
Solution
Using the following settings to achieve better design results:
Synthesis settings:
- Option -control_set_opt_threshold 0
- Option -fsm_extraction sequential
- Use this TCL switch:
set_param synth.elaboration.rodinMoreOptions " set rt::extractNetlistGenomes false"
Implementation settings:
- Strategy: Area_Explore
3.3.1.3 EtherCAT IP Core is not part of the IP Catalog
The EtherCAT IP Core is not part of the IP Catalog, because the configuration options required by the EtherCAT IP Core are currently not supported by the IP Packager/IP Catalog until Vivado 2014.3. Additionally, Vivado does not
support Spartan-6 FPGA devices, so ISE support is still required. Maintaining two types of configuration (IPCore_Config tool for ISE and IP Catalog for Vivado) is currently not planned.
Solution
Use The IPCore_Config tool to configure the EtherCAT IP Core, then add it to your project. You can either instantiate the EtherCAT IP Core wrapper directly, or you can use the IP Packager to add it to the IP Catalog (without any
configuration options). The last solution allows for automatically connecting the AXI interface.