BECKHOFF EtherCAT IPCore Section III - Manual (Page 12)

EtherCAT IP Core for Xilinx FPGAs
Slave Controller – EtherCAT IP Core Data Sheet Addendum 9
3.3.2 Vivado 2015
3.3.2.1 Vivado 2015.1: The resource consumption (Slice LUTs) of the EtherCAT IP Core is too high
The EtherCAT IP Core has a higher resource consumption with Vivado 2015.1 compared with Vivado 2014.3. The number of Slice LUTs may be about 10% higher.
Solution
Use a previous version.
3.3.2.2 Vivado 2015.1: ZC702_AXI_VIVADO example design invalid constraints
Vivado 2015.1 has renamed clock signals inside the Zynq block design. This causes some constraints to fail with such an error message:
[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_clocks CLKOUT1]'.
Solution
In the ZC702.xdc constraint file, rename all clock references using
CLKOUT1
to the new name
clk_out1_ZYNC_BLOCK_clk_wiz_0_0
3.3.2.3 Vivado 2015.1: ZC702_AXI_VIVADO example design does not meet timing requirements
Vivado introduces BUFGs on the MII_TX_CLK wires, which causes timing failures for paths from ISMNET1_PHY1_MII_TX_CLK and ISMNET1_PHY2_MII_TX_CLK. In addition, it causes suboptimal placement of other signals in the IP
core, which may cause additional timing violations.
Solution
Add this line to the ZC702.xdc constraints file:
set_property BUFFER_TYPE NONE [get_ports ISMNET1_PHY*_MII_TX_CLK]
3.3.2.4 Vivado 2015.1: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK
Vivado 2015.1 generates an xparameters.h file without base address defines if the EtherCAT IP core (and probably any other AXI slave) is connected externally to the Zynq block design. This causes a compile error for the example
software in the SDK:
../src/EtherCAT_TestApp.c:18:28: error: 'XPAR_ETHERCAT_AXI_BASEADDR' undeclared (first use in this function)
Solution
Change the base address reference in EtherCAT_TestApp.c (line 18) to refer to the actual base address instead of the XPAR_ETHERCAT_AXI_BASEADDR define:
#define ETHERCAT_BASEADDR 0x43C00000