Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 20)

6–2 Chapter 6: Board Test System
Using the Board Test System
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
User Guide
1 On Windows, click Start > All Programs > Altera > Stratix V GX 100G Development
Kit
<version> > Board Test System to run the application.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA.
c
If using the optic modules (CFP, SFP, QSFP) you must set the user switch SW4.7 to
enabled (1) to turn on the laser. When done using the optics, set SW4.7 to disabled (0).
Using the Board Test System
This section describes each control in the Board Test System application.
1
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
® II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
The Configure Menu
Use the Configure menu ( Figure 6–1 ) to select the design you want to use. Each design
example tests different functions that corresponds to one or more application tabs.
To configure the FPGA with a test system design, perform the following steps:
1. On the Configure menu, click the configure command that corresponds to the
functionality you wish to test.
2. In the dialog box that appears, click Configure or Download Start to download
the corresponding design’s Raw-Binary Format (.rbf) configuration file to the
FPGA. The download process usually takes about a minute.
3. When configuration finishes, close the Quartus II Programmer if open. The design
begins running in the FPGA. The corresponding GUI application tabs that
interface with the design are now enabled.
Figure 6–1. The Configure Menu