Altera Unique Chip ID - Manual (Page 8)

Example 1: Upgrading IP Cores at the Command Line
You can upgrade IP cores that support auto upgrade at the command line. IP cores that do not
support automatic upgrade do not support command line upgrade.
• To upgrade a single IP core that supports auto-upgrade, type the following command:
quartus_sh –ip_upgrade –variation_files .
Example:
quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx
• To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following
command:
quartus_sh –ip_upgrade –variation_files “.;
.”
Example:
quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v" hps_testx
IP cores older than Quartus II software version 12.0 do not support upgrade. Altera
verifies that the current version of the Quartus II software compiles the previous Note:
version of each IP core. The Altera IP Release Notes reports any verification exceptions
for Altera IP cores. Altera does not verify compilation for IP cores older than the
previous two releases.
Related Information
Altera IP Release Notes
Migrating IP Cores to a Different Device
IP migration allows you to target the latest device families with IP originally generated for a different device.
Some Altera IP cores require individual migration to upgrade. The Upgrade IP Components dialog box
prompts you to double-click IP cores that require individual migration.
1. To display IP cores requiring migration, click Project > Upgrade IP Components. The Description field
prompts you to double-click IP cores that require individual migration.
2. Double-click the IP core name, and then click OK after reading the information panel.
The parameter editor appears showing the original IP core parameters.
3. For the Currently selected device family, turn off Match project/default, and then select the new target
device family.
4. Click Finish, and then click Finish again to migrate the IP variation using best-effort mapping to new
parameters and settings. Click OK if you are prompted that the IP core is unsupported for the current
device. A new parameter editor opens displaying best-effort mapped parameters.
5. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog is the parameter
editor default HDL for synthesis files. If your original IP core was generated for VHDL, select VHDL to
retain the original output HDL format.
Altera Unique Chip ID IP Core User Guide Altera Corporation
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Migrating IP Cores to a Different Device 8
2014.09.02