Avalue ESM-CDV - Manual (Page 33)

ESM-CDV User ’s Manual
ESM-CDV User ’s Manual 33
2.4.3.1 Signal Description
– COM Express Connector 2 (CN1B)
2.4.3.1.1 PCI Signals
Signal Signal Description
PCI_AD[0:31] PCI bus multiplexed address and data lines.
PCI_C/BE[0:3]# PCI bus byte enable lines, active low.
PCI_DEVSEL# PCI bus Device Select, active low.
PCI_FRAME# PCI bus Frame control line, active low.
PCI_IRDY# PCI bus Initiator Ready control line, active low.
PCI_TRDY# PCI bus Target Ready control line, active low.
PCI_STOP# PCI bus STOP control line, active low, driven by cycle initiator.
PCI_PAR PCI bus parity.
PCI_PERR# Parity Error: An external PCI device drives PERR# when it receives data that has a
parity error.
PCI_REQ[0:3]# PCI bus master request input lines, active low.
PCI_ GNT[0:3]# PCI bus master grant output lines, active low.
PCI_RESET# PCI Reset output, active low.
PCI_LOCK# PCI Lock control line, active low.
PCI_SERR# System Error: SERR# may be pulsed active by any PCI device that detects a system
error condition.
PCI_PME# PCI Power Management Event: PCI peripherals drive PME# to wake system from
low-power states S1-S5.
PCI_CLKRUN# Bidirectional pin used to support PCI clock run protocol for mobile systems.
PCI_IRQ[A:D]# PCI interrupt request lines.
PCI_CLK PCI 33MHz clock output.
2.4.3.1.2 IDE Signals
Signal Signal Description
IDE_D[0:15] Bidirectional data to / from IDE device.
IDE_A[0:2] Address lines to IDE device.
IDE_LOW# I/O write line to IDE device.
Data latched on trailing (rising) edge.
IDE_IOR# I/O read line to IDE device.
IDE_REQ IDE Device DMA Request.
It is asserted by the IDE device to request a data transfer.
IDE_ACK# IDE Device DMA Acknowledge.