Avalue ESM-CDV - Manual (Page 26)

ESM-CDV User ’s Manual
26 ESM-CDV User ’s Manual
2.4.2.1.4 Flat Panel LVDS Signals
Signal Signal Description
BIASON Controls panel contrast voltage.
DIGON Controls panel digital power.
ENBKL# Controls backlight power enable.
I
2
C_DAT, I
2
C_CLK
I
2
C interface for panel parameter EEPROM. This EERPOM is mounted on the
LVDS receiver. The data in the EEPROM allows the EXT module to automatically
set the proper timing parameters for a specific LCD panel.
2.4.2.1.5 LPC Signals
Signal Signal Description
LPC_FRAME# LPC frame indicates the start of an LPC cycle
LPC_AD[0:3] LPC multiplexed address, command and data bus
LPC_DRQ[0:1]# LPC serial DMA request
LPC_CLK LPC clock output - 33MHz nominal
LPC_SERIRQ LPC serial interrupt
2.4.2.1.6 Miscellaneous Signals
Signal Signal Description
I
2
C_CK General purpose I
2
C port clock output
I
2
C_DAT General purpose I
2
C port data I/O line
SPKR Output for audio enunciator - the "speaker" in PC-AT systems
KBD_RST# Input to Module from (optional) external keyboard controller that can force a reset.
KBD_A20GATE Input to Module from (optional) external keyboard controller that can be used to control the CPU A20 gate line.
BIOS_DIS0#
BIOS_DIS1#
Selection straps to determine the BIOS boot device
BIOS_DIS1# BIOS_DIS0#
Chipset
SPI CS1#
Destination
Chipset
SPI CS0#
Destination
Carrier
SPI_CS#
SPI
Descriptor
Bios Entry
Ref
Line
1 1 Module Module High Module SPI0/SPI1 0
1 0 Module Module High Module
Carrier
FWH
1
0 1 Module Carrier SPI0 Carrier SPI0/SPI1 2
0 0 Carrier Module SPI1 Module SPI0/SPI1 3
KB_RST# Input to module from (optional) external keyboard controller that can force a reset.
KB_A20GATE Input to module from (optional) external keyboard controller that can be used to control the CPU A20 gate line.