ADLINK cPCI-8554/R - Manual (Page 37)

Registers •27
3.3 Timer/Counter Registers
The 8254-chips occupies 4 I/O address locations on the cPCI/PCI-8554/R
as shown below. Users can refer to Tundra's or Intel's data sheet for a full
description of the 8254 features available at the following websites:
“http://support.intel.com/support/controllers/peripheral/231164.htm” or
http://www.tundra.com (for Tundra’s 82C54 datasheet.)
Address: BASE + 0x00 ~ BASE + 0x0F
Attribute: read / write
Data Format:
Base + 0 Counter 1 Register (R/W)
Base + 1 Counter 2 Register (R/W)
Base + 2 Counter 3 Register (R/W)
Base + 3
8254 Mode Control Register (W)
8254 Read Back Register (R)
Base + 4 Counter 4 Register (R/W)
Base + 5 Counter 5 Register (R/W)
Base + 6 Counter 6 Register (R/W)
Base + 7
8254 Mode Control Register (W)
8254 Read Back Register (R)
Base + 8 Counter 7 Register (R/W)
Base + 9 Counter 8 Register (R/W)
Base + A Counter 9 Register (R/W)
Base + B
8254 Mode Control Register (W)
8254 Read Back Register (R)
Base + C Counter 10 Register (R/W)
Base + D Counter 11 Register (R/W)
Base + E Counter 12 Register (R/W)
Base + F
8254 Mode Control Register (W)
8254 Read Back Register (R)
Table 5. Timer/Counter Registers
3.4 Timer / Counter Clock Mode Control