ADLINK PXI-2006 - Manual (Page 78)

68 Operation Theory
In PCI form factor, there is a connector on the top right corner of
the card for the SSI. Refer to section 2.3 for the connector posi-
tion. All the SSI signals are routed to the 20-pin connector from the
FPGA. To synchronize multiple cards, users can connect a special
ribbon cable (ACL-SSI) to all the cards in a daisy-chain configura-
tion
In PXI form factor, we utilize the PXI trigger bus built on the PXI
backplane to provide the necessary timing signal connections. All
the SSI signals are routed to the P2 connector. No additional cable
is needed. For detailed information of the PXI specifications,
please refer to PXI specification Re-vision 2.0 from PXI System
Alliance (www.pxisa.org).
The 6 internal timing signals could be routed to the SSI or the PXI
trigger bus through software drivers. Please refer to section 4.6.1
for detailed in-formation of the 6 internal timing signals. Physically
the signal routings are accomplished in the FPGA. Cards that are
connected together through the SSI or the PXI trigger bus, will still
achieve synchronization on the 6 timing signals.
The mechanism of the SSI/PXI
1. We adopt master-slave configuration for SSI/PXI. In a
system, for each timing signal, there shall be only one
master, and other cards are SSI slaves or with the SSI
function disabled.
2. For each timing signal, the SSI master doesn’t have to
be in a single card.