Compaq 3000 - Manual (Page 40)

Chapter 2. RAID Array Controller
EK–SMCPQ–UG. C01 2–7
2.5 Performance Enhancements
The controller employs a number of techniques to achieve as much performance
as possible from its design.
2.5.1 Custom Components
To increase performance and reliability, the controller’s core functions have been
encapsulated in four custom ASIC (Application Specific Integrated Circuits)
components as follows:
XOR ASIC: Used in the Exclusive -Or parity calculations employed by RAID
levels 4 and 5.
DMA ASIC: Controls the data path hardware for the various I/O ports
CPU Interface ASIC: Supports the controller’s MIPS R3000 RISC central
processing unit.
Memory Controller ASIC: Controls the memory system and supports data
movement on the internal bus at a maximum burst rate of 80 MB/second and a
maximum sustainable rate of 60 MB/second.
2.5.2 Efficient Write and Read Algorithms
Standard RAID write operations that involve parity, such as those in RAID levels
4 and 5, require multiple, time-consuming steps:
1. Read data from the parity drive.
2. Read existing data from the target data drives.
3. Exclusive-Or the old parity, old data, and new data to generate new parity
data.
4. Write the new parity data to the parity drive.
5. Write the new data to the target data drives.
The controller uses several techniques to streamline write operations and signifi-
cantly improve performance. All the techniques use the controller’s on-board
cache 60-nanosecond SIMMs.
NOTE
The controller will not operate without at least one
16 MB SIMM installed in its cache. Nor will it op-
erate without an un-interruptable power supply
connected to the controller. Without a UPS, data
stored in the cache, but not yet written to the disk
drives, would be lost in the event of a power inter-
ruption.