Cypress CYV15G0404DXB - Manual (Page 30)

CYV15G0404DXB
Document #: 38-02097 Rev. *B Page 30 of 44
t
RISE
[20]
CML Output Rise Time 20
−80% (CML Test Load)
SPDSELx = HIGH 60 270 ps
SPDSELx = MID 100 500 ps
SPDSELx =LOW 180 1000 ps
t
FALL
[20] CML Output Fall Time 80
−20% (CML Test Load)
SPDSELx = HIGH 60 270 ps
SPDSELx = MID 100 500 ps
SPDSELx =LOW 180 1000 ps
t
DJ
[20, 29, 31]
Deterministic Jitter (peak-peak)
[32]
IEEE 802.3z 27 ps
Z
RJ
[20, 30, 31]
Random Jitter (
σ
)
[32]
IEEE 802.3z 11 ps
t
REFJ
[20] REFCLKx jitter tolerance / Phase noise limits TBD
t
TXLOCK
Transmit PLLx lock to REFCLKx± 200
μs
CYV15G0404DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
t
RXLOCK
Receive PLL lock to input data stream (cold start) 376k UI
Receive PLL lock to input data stream 376k UI
t
RXUNLOCK
Receive PLL Unlock Rate 46 UI
t
JTOL
[20]
Total Jitter Tolerance
[32]
IEEE 802.3z 600 ps
t
DJTOL
[20]
Deterministic Jitter Tolerance
[32]
IEEE 802.3z 370 ps
Capacitance [20]
Parameter Description Test Conditions Max. Unit
C
INTTL
TTL Input Capacitance T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V 7 pF
C
INPECL
PECL input Capacitance T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V 4 pF
CYV15G0404DXB AC Electrical Characteristics (continued)
Parameter Description Min. Max Unit
CYV15G0404DXB HOTLink II Transmitter Switching Waveforms
TXCLKx
TXDx[7:0],
TXCTx[1:0],
t
TXDH
t
TXDS
t
TXCLK
t
TXCLKH
t
TXCLKL
Transmit Interface
Write Timing
TXCLKx selected
REFCLKx
Transmit Interface
t
REFCLK
t
REFH
t
REFL
t
TREFDS
t
TREFDH
Write Timing
TXRATEx = 0
TXDx[7:0],
TXCTx[1:0],
REFCLKx selected
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