Cypress FX2LP User Manual
Page 12
February 19, 2008
Document No. 001-15342 Rev. **
12
AN6077
// RDY0=1, when peripheral is "not empty"
// drive FIFOADDR lines
OEA = 0xC0;
IOA = 0x00;
if( EP68FIFOFLGS & 0x01 )
{
// EP6FF=1, when fifo "full"
}
else
{
// EP6FF=0, when fifo "not full", for example, buffer available
// setup GPIF transaction count
SYNCDELAY;
EP6GPIFTCH = 0x02;
SYNCDELAY;
EP6GPIFTCL = 0x00;
// trigger FIFO read transaction(s), using SFR
SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
// wait for the transaction to terminate naturally
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) )
{
; // poll GPIFTRIG.7, DONE bit
}
// AUTOOUT=1, core handles transfers
// cpu is not in the data path
// however, cpu is responsible for committing "short packets"
xFIFOTC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL );
if( xFIFOTC_IN < enum_pkt_size )
{
// handle short packet from peripheral
SYNCDELAY;
INPKTEND = 0x06; // w/skip=0;commit however many bytes in packet.
SYNCDELAY;
}
else
{
// core commits packet via EPxAUTOINLENH/L registers
}
}
}
else
{
// master has all the data the peripheral sent
}
}
else
{
// peripheral interface busy
}
}