Maxim Integrated 78M6631 - Manual (Page 12)

78M6631 Firmware Description Document UG_6631_078
12 Rev 2
2.2.7 Power Factor Calculation
The 78M6631 provides a direct power factor measurement simultaneously for phase A, phase B, and
phase C. Power factor in an AC circuit is defined as the ratio of the active power flowing to the load to the
apparent power. The power factor measurement is defined in terms of “import” or “export” referring to the
direction of the power in the system.
Power factor is reported for all phases, and a weighted average is also provided. All values will be
between -1.0 and +1.0 and can be scaled by the user to the desired resolution.
2.2.8 Line Frequency
Frequency (FREQ) is both an input register and an output (result) register (low-rate). If the bit
”FREQ” (Command Register bit 4) is set to 0, the line frequency (measured from a phase reference)
is stored in this variable. If bit ”FREQ” is instead set to 1, the value contained in this register will be
utilized by the firmware. The default value is in this case 60Hz, and can be modified by the user.
This variable is used to set the frequency of the sine/cosine generator for fundamental and harmonic
calculations. It can also be set to a harmonic or an arbitrary unrelated frequency to measure the
amplitude of that frequency.
Phase Reference: The phase reference is calculated on the difference VA-VB-VC.
2.2.9 Accumulation Interval
The low-rate calculation/results are performed over a time interval referred as accumulation interval. The
accumulation interval can be modified by the user through Accum Register. The Accum register is an
unsigned integer containing the minimum number of high-rate samples that define the low-rate interval.
For example, with a value of 0x7D0 the accumulation interval results in:
Accumulation Inteval =
1
𝑆𝑎𝑚𝑝𝑙𝑒 𝑅𝑎𝑡𝑒 ∗ Accum
Resulting in an accumulation interval of 793 ms.
Effective Accumulation Interval
The register Divisor reports the value of the effective accumulation interval as number of high-rate
samples. Referring to the processing flow diagrams, it represents the divisor (N) for low-rate accumulated
results.
Line-Lock
The Command Register bit “LINELOCK” can be used to lock the low-rate interval to incoming Line
Voltage Cycles. When set, the low-rate sample period will end after the first low-to-high zero crossing of
the Phase A Voltage input occurs after the Minimum Accumulation time has elapsed. The Actual
Accumulation Interval will span an integer number of line cycles.
When LINELOCK is not set, the Accumulation Interval will equal the number of high rate samples
specified in the Accum register.
2.2.10 Zero Crossing Detector
The polarity of the Phase Reference is used by the zero-crossing detection logic to determine the
start and end of consecutive line cycles. It is used for frequency measurement, to determine the
backstep for quadrature voltage delay lines, and to lock the low-rate computation cycle to the line
frequency. A 3/4-cycle holdoff timer is used to prevent noise and harmonics from registering as
additional zero crossings.