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Cypress CY62167DV18 User Manual

Mbit (1m x 16) static ram, Features, Functional description

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16-Mbit (1M x 16) Static RAM

CY62167DV18 MoBL

®

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05326 Rev. *C

Revised April 25, 2007

Features

• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power

— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f

max

• Ultra low standby power
• Easy memory expansion with CE

1

, CE

2

, and OE features

• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package

Functional Description

[1]

The CY62167DV18 is a high performance CMOS static RAM

organized as 1M words by 16 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life

™ (MoBL

®

) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption by 99% when addresses are not

toggling. Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE

1

HIGH

or CE

2

LOW or both BHE and BLE are HIGH). The input and

output pins (IO

0

through IO

15

) are placed in a high impedance

state when:

• Deselected (CE

1

HIGH or CE

2

LOW)

• Outputs are disabled (OE HIGH)
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)

are disabled (BHE, BLE HIGH)

• Write operation is active (CE

1

LOW, CE

2

HIGH and WE

LOW)

To write to the device, take Chip Enables (CE

1

LOW and CE

2

HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then

data from IO pins (IO

0

through IO

7

) is written into the location

specified on the address pins (A

0

through A

19

). If BHE is LOW

then data from IO pins (IO

8

through IO

15

) is written into the

location specified on the address pins (A

0

through A

19

).

To read from the device, take Chip Enables (CE

1

LOW and

CE

2

HIGH) and OE LOW while forcing the WE HIGH. If BLE

is LOW, then data from the memory location specified by the

address pins appear on IO

0

to IO

7

. If BHE is LOW, then data

from memory appears on IO

8

to IO

15

. See the

“Truth Table” on

page 9

for a complete description of read and write modes.

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at

http://www.cypress.com

.

Logic Block Diagram

1M × 16

RAM Array

IO

0

–IO

7

ROW DECODER

A

8

A

7

A

6

A

5

A

2

COLUMN DECODER

A

11

A

12

A

13

A

14

A

15

SENSE AMPS

DATA IN DRIVERS

OE

A

4

A

3

IO

8

–IO

15

WE

BLE

BHE

A

16

A

0

A

1

A

17

A

9

A

18

A

10

CE

2

CE

1

A

19

BYTE

Power Down

Circuit

BHE
BLE

CE

2

CE

1

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