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Cypress CY7C1218H User Manual

Mbit (32k x36) pipelined sync sram, Features, Functional description

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1-Mbit (32K x36) Pipelined Sync SRAM

CY7C1218H

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05667 Rev. *B

Revised July 6, 2006

Features

• Registered inputs and outputs for pipelined operation

• 32K × 36 common I/O architecture

• 3.3V core power supply (V

DD

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

®

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1218H SRAM integrates 32K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

1

), depth-expansion Chip Enables (CE

2

and CE

3

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.

The CY7C1218H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

Q1

Q0

ADSP

ADSC

MODE

BWE

GW

CE

1

CE

2

CE

3

OE

ENABLE

REGISTER

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

E

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

BW

B

BW

C

BW

D

BW

A

MEMORY

ARRAY

SLEEP

CONTROL

ZZ

A

[1:0]

2

DQ

A

,DQP

A

BYTE

WRITE REGISTER

DQ

B,

DQP

B

BYTE

WRITE REGISTER

DQ

C

,DQP

C

BYTE

WRITE REGISTER

DQ

D,

DQ

D

BYTE

WRITE REGISTER

DQ

A,

DQP

A

BYTE

WRITE DRIVER

DQ

B,

DQP

B

BYTE

WRITE DRIVER

DQ

C

,DQP

C

BYTE

WRITE DRIVER

DQ

D

,DQP

D

BYTE

WRITE DRIVER

DQP

A

DQP

B

DQP

C

DQP

D

DQs

Logic Block Diagram

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