Digilent Memory Module 1 - Manual (Page 2)

MEM1 Reference Manual Digilent, Inc.
www.digilentinc.com page 2 of 3
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A memory write cycle is preformed by placing
the address and data on the address and data
lines, bringing the appropriate chip select line
low and then writing the data by bringing the
WE line low and then high.
Please refer to the manufacturers’ data sheets
for the memory devices for exact wave forms
and timing requirements for read and write
cycles.
Flash Memory Operation
Read operations on the flash memory are
performed similarly to read operations on the
SRAM. The timing of write operations on the
flash memory is similar to the timing of write
operations on the SRAM, however, there are
additional considerations for writing flash
memory.
The flash memory device is divided into
multiple blocks of varying sizes. A block must
be erased before locations within that block
can be written. When a block is erased, all
memory locations within that block are set to
the value 0xFF (all bits 1). When writing to the
flash memory, a 1 bit can be written to a 0, but
a 0 bit can not be changed back to a 1 except
by erasing the entire block. Writing a 0 over the
top of a bit whose value is already 0 will lead to
wear-out of the device and should be avoided.
In general, only bytes whose value is 0xFF
should be written to.
A block erase is performed by writing the erase
command sequence to any address within the
block. A block erase can take several
milliseconds to complete and the device status
should be checked to ensure that the erase
has completed before attempting to issue
another erase command sequence or a write
command sequence to the device.
A location in the flash memory is written by
writing the write command sequence to the
address of the location to be written. Similarly
to the erase command, a write command takes
several microseconds to complete and the
device status should be checked to ensure that
the write has completed before initiating another
write operation.
Power Supplies
The MEM1 draws power from two pins on the
40-pin interface connector: pin 37 supplies 3.3V;
pin 39 provides system GND. Pin 40 supplies
unregulated voltage (VU) from the system board,
however, VU is not used on the MEM1.
Expansion Connector
Connector pinouts are shown below. Separately
available tables show FPGA pin connections for
the devices on the MEM1 when it is attached to
various Digilent system boards.
Note that connectors on system boards and
peripheral boards use the same numbering
scheme – that is, if the board is held with the
component side towards you and the connectors
pointing up, then pin #1 is always on the bottom
left corner of the connector.
This means that when a peripheral board is
plugged into a system board, the numbering
patterns are mirrored. Pin #1 on the peripheral
board mates with pin #39 on the system board,
peripheral board pin #2 mates with system pin
#40, etc. Note that odd pin number mating pairs
add to 40, and even pin number mating pairs
add to 42 (so pin 36 mates with pin 6, pin 27
mates with pin 13, etc.).