Cypress CY7C138 - Manual (Page 8)

CY7C138, CY7C139
Document #: 38-06037 Rev. *D Page 8 of 17
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port) [22, 24, 25]
Figure 8. Semaphore Read After Write Timing, Either Side [26]
Switching Waveforms
(continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
t
LZOE
SEM OR CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
t
AW
t
WC
t
SCE
t
SA t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
SEM OR CE
R/W
DATA OUT
DATA IN
t
LZWE
DATA VALID
ADDRESS
Notes
20. BUSY = HIGH for the writing port.
21. CE
L
= CE
R
= LOW.
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off
and data to be placed on the bus for the required t
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not
apply and the write pulse can be as short as the specified t
PWE
.
24. R/W must be HIGH during all address transitions.
[+] Feedback