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Switching characteristics – Cypress CY7C1344H User Manual

Page 9

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CY7C1344H

Document #: 001-00211 Rev. *B

Page 9 of 15

Switching Characteristics

Over the Operating Range

[10, 11]

Parameter

Description

133 MHz

100 MHz

Unit

Min.

Max.

Min.

Max.

t

POWER

V

DD

(Typical) to the First Access

[12]

1

1

ms

Clock

t

CYC

Clock Cycle Time

7.5

10

ns

t

CH

Clock HIGH

2.5

4.0

ns

t

CL

Clock LOW

2.5

4.0

ns

Output Times

t

CDV

Data Output Valid after CLK Rise

6.5

8.0

ns

t

DOH

Data Output Hold after CLK Rise

2.0

2.0

ns

t

CLZ

Clock to Low-Z

[13, 14, 15]

0

0

ns

t

CHZ

Clock to High-Z

[13, 14, 15]

3.5

3.5

ns

t

OEV

OE LOW to Output Valid

3.5

3.5

ns

t

OELZ

OE LOW to Output Low-Z

[13, 14, 15]

0

0

ns

t

OEHZ

OE HIGH to Output High-Z

[13, 14, 15]

3.5

3.5

ns

Set-up Times

t

AS

Address Set-up before CLK Rise

1.5

2.0

ns

t

ADS

ADSP, ADSC Set-up before CLK Rise

1.5

2.0

ns

t

ADVS

ADV Set-up before CLK Rise

1.5

2.0

ns

t

WES

GW, BWE, BW

[A:D]

Set-up before CLK Rise

1.5

2.0

ns

t

DS

Data Input Set-up before CLK Rise

1.5

2.0

ns

t

CES

Chip Enable Set-up

1.5

2.0

ns

Hold Times

t

AH

Address Hold after CLK Rise

0.5

0.5

ns

t

ADH

ADSP, ADSC Hold after CLK Rise

0.5

0.5

ns

t

WEH

GW, BWE, BW

[A:D]

Hold after CLK Rise

0.5

0.5

ns

t

ADVH

ADV Hold after CLK Rise

0.5

0.5

ns

t

DH

Data Input Hold after CLK Rise

0.5

0.5

ns

t

CEH

Chip Enable Hold after CLK Rise

0.5

0.5

ns

Notes:

10. Timing reference level is 1.5V when V

DDQ

= 3.3V and 1.25V when V

DDQ

= 2.5V.

11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above V

DD

(minimum) initially before a Read or Write operation

can be initiated.

13. t

CHZ

, t

CLZ

, t

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

14. At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

15. This parameter is sampled and not 100% tested.

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