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E-keying, 1 pci express lane width – x4 or x1, 2 pci express reference clock – Kontron AM5030 IPMI User Manual

Page 36: 1 clock receiver, Clock receiver, Ipmi firmware user guide am5030

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IPMI Firmware User Guide

AM5030

Page 36

ID: 1042-7364, Rev. 1.0

7.

E-Keying

E-Keying has been defined in the AMC.0 R2.0 Specification to prevent module damage or
improper operation, and to verify bay connection compatibility. Therefore the FRU Data of an
AMC module contains PICMG defined records which describe the module’s AMC
interoperability:

• Module Current Requirements Record

• Clock Configuration Record, for the PCI-Express reference clock

• AMC Point-to-point record, describing module’s AMC port capabilities

The IPMI commands ‘Set AMC Port State’ and ‘Get AMC Port State’ defined by the AMC.0
specification are used by the carrier or MCH for either granting or rejecting the E-keys (i.e.
enabling or disabling of AMC Ports during E-Keying).

Which AMC port connections are activated will be decided during E-keying. The information
which AMC port is enabled or not, can be directly read from board’s E-Keying Configuration
registers (IAKEY0 and IAKEY1) at addresses 298h / 299h.
The ‘DIP Switch SW2’ can be used to forcibly disable some AMC Ports if required. Please refer
to the “AM5030 User Guide” for details.

7.1

PCI Express Lane Width – x4 or x1

The AM5030 supports either one PCI-E x4 connection (default) or one PCI-E x1 connection
alternatively. Both PCI-E Gen1 and PCI-E Gen2 frequencies are supported.

7.2

PCI Express Reference Clock

Both sides (Root Complex and Endpoint) of a PCI-Express connection should be driven by a
common reference clock. The PCI-E reference clock may be generated locally by the module
or acquired from the AMC connector.

The AM5030 (PCI-Express Root Complex) may act either as clock receiver or as clock
source. This is described by the Clock Configuration Record (for the PCI-Express reference
clock) and defined by the “AMC.1 R2.0, PCI Express on AMC” specification.

7.2.1

Clock Receiver

The PCI-E reference clock provided by the carrier may be slightly modulated (SSC - Spread
Spectrum Clock). The FRU E-Keying data for AM5030 contains several AMC Link Descriptors
for the PCI-Express channel, describing either SSC or non-SSC and the PCI-E Gen2 or Gen1
clock capabilities.

The carrier's IPMC or the MCH selects the 'matching' Link descriptor (SSC / non-SSC and
Gen2/Gen1) during E-keying using the 'Set AMC Port State' command.