Achronix Speedster22i LaneLinx - Manual (Page 9)

UG035 (v1.0), March 19, 2012 9
Reference Design
The Reference Design consists of two blocks, TX_data_gen and RX_data_comp.
1. TX_data_gen:
This block generates data which is transmitted through a parallel interface to the
LaneLinx Macro. The block also generates Start-of-Packet and End-of-Packet signals
depending on whether the signal “tx_ready” is asserted by XG_LaneLinx block.
2. RX_data_comp:
After transmission has completed the LaneLinx protocol does the RX-data comparison to
see that the RX side packet reception is OK or not. If the RX data is validated this block
asserts “compare_ok” signal saying that the data is good, otherwise it asserts bad-data
indicator.
Revision History
The following table shows the revision history for this document.
Date Version Revisions
3/19/2012 1.0 Initial Achronix release.