Achronix Speedster22i LaneLinx - Manual (Page 3)

UG035 (v1.0), March 19, 2012 3
Introduction
LaneLinx TM is a lightweight, multi-gigabit per second serial protocol. It enables high bandwidth, serial
connectivity with minimal programmable resource requirements, enabling lightweight, high performance data
links between Speedster22i devices. This communication protocol goes through a number of steps to establish a
reliable link. Once the link is established, data is transmitted and received. Each packet of data is preceded with
SOP (Start-Of-Packet) and ends with EOP (End-Of-Packet) identifiers. LaneLinx is a single channel protocol, i.e. it
uses only a single SerDes Tx/Rx lane. By leveraging the Speedster22i embedded PCS resources, the minimum
amount of programmable (LUT based) Resources.
This User Guide covers the 2.5Gbps version of LaneLinx. Other speeds are available and have near identical
construction.
LaneLinx Overview
The LaneLinx Macro has 4 main sub-components contained within the top level RTL (XG_Lanelinx)
1. LaneLinx2p5G – the HardIP SerDes instantiation
2. TX_data_module
3. RX_data_module
4. Link_FSM block
The LaneLinx Macro is delivered with a reference design which provides a sample instantiation of XG_Lanelinx
connected to data generation and data compare blocks. When a SerDes loopback is used, (in simulation or in real
hardware), the data generation and compare blocks are self-checking. The data generation and data compare
blocks also include data packetization (start of packet and end of packet), and important part of the protocol
Figure 1 below shows the blocks within the XG_Lanelinx macro and how the reference design components are
connected to the Macro.