Achronix Speedster22i LaneLinx - Manual (Page 7)

UG035 (v1.0), March 19, 2012 7
The Link_Training block
This block generates the training signal for linking up the channel at the required data-rate. This
block generates the transmit data and control signals, which depend on the SKIP, SYNC and
SEQUENTIAL-PATTERN values. This block is also a multiplexor between the link training pattern
and link initialization pattern controlled by the Link_FSM block.
The signal from the SerDes macro “lane0_o_rx_syma_locked” (which is called “serdes_aligned” in
this block) is used to generate the training order pattern. The training pattern is “9C4A”.
TX_data_module
Upon receiving the data, Start-Of-Packet, End-Of-Packet and transmit data valid signals from the
external interface (e.g. TX_data_gen block or custom user interface) the transmit-ready signal is
generated, as well as the transmit control signal and the 16-bit parallel data values will be generated
to transmit to the SerDes block. The generated transmit ready signal will be propagated to the
external interface in this reference design “tx_data_gen” block.
RX_data_module:
This block receives the aligned 16-bit parallel data, control signal and link initialized signal value
from the Link_FSM block. Upon receiving these signals this block will generate Start-Of-Packet, End-
Of-Packet, the properly aligned 16-bit data, receive data valid signal for the external interface (in this
reference design it is “RX_data_compare” block).