Cypress CY7C1215H - Manual (Page 15)

CY7C1215H
Document #: 38-05666 Rev. *B Page 15 of 15
Document History Page
Document Title: CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM
Document Number: 38-05666
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 343896 See ECN PCI New Data Sheet
*A 430678 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for V
DDQ
relative to GND
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Modified test condition from V
IH
< V
DD
to V
IH
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
*B 481916 See ECN VKN Converted from Preliminary to Final.
Updated the Ordering Information table.
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