Pi33xx-2x i, C digital interface guide, Q1 q2 clamp switch vs – Vicor PI33XX-2X I2C Digital Interface Guide User Manual
Page 13
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PI33XX-2X I
2
C Digital Interface Guide
T4: After Q2 turns off, the clamp switch turns on to preserve the energy stored in the inductor to be used for the
next T1, while clamping VS to Vout. At the end of T4 and beginning of T1, the clamp switch opens and the parasitic
capacitance of Q1 and Q2 resonates with the output inductor to provide zero voltage switching.
The rising edge of SYNCO defines the beginning of T1 and can be observed in Figure 13. The rising edge of SYNCO is
synchronized to SYNCI rising or falling edge as programmed plus any delay desired. Figure 13 shows the timing
relationship of SYNCO, SYNCI and the phase node VS with default timing and phase delay. Note that the node VS in
the schematic of Figure 12 is called VS1 in Figure 13 and can be observed on channel 3 of the plot.
Figure 12 - ZVS Buck Topology Timing Diagram
= Clamp open
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Sync at T1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
Vout
Vin
ON
ON
ON
ON
ON
ON
I_L
Iout
IQ1
= Clamp open
= Clamp open
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Vout
Q1
Q2
Cin
Cout
VS
LS
Driver
HS
Driver
ZVS-Buck
Vin
Clamp
Switch
Sync at T1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
Vout
Vin
ON
ON
ON
ON
ON
ON
I_L
Iout
IQ1
T1
T3
T4
Q1
Q2
CLAMP
SWITCH
VS
Vout
Vin
ON
ON
ON
ON
ON
ON
I_L
Iout
IQ1