Despatch Protocol Plus Modbus Communications - Manual (Page 21)

Chromalox Instruments and Controls
A-51643 Rev. 6 10/06/03 15
4 Application Operations
This section defines application operations in Protocol
TM
Plus controller and how they are achieved
through Modbus.
4.1 Security Level and Discrete Inputs, Discrete Outputs, and Register Access
Access to discrete I/O and registers addresses are guarded via a security level. The communications
security code holding register ($0000) contains the current security setting for accessing data in the
controller through the communications port. Each I/O or register address has an associated preset security
level that controls access. If the current communication security code does not match the register‘s
security level, access is denied. An illegal data address exception is generated and data is not changed.
For multiple reads and writes, if any address is inaccessible, an exception response occurs and data is not
affected in the slave.
The communications security operation mirrors the security operation for adjusting parameters through
the front panel keypad. Security levels for each I/O and register address are shown in the I/O and register
mapping tables. The access passwords for security levels 1 and 2 are set via the security level holding
registers ($0008, $0009). The communications security code is set to 0 whenever the controller is
powered up or reset. The access password registers ($0008, $0009) cannot be written to while the
controller is in setup mode to protect adjustments in progress via the front panel keypad.
Table 7: Communication Security Levels
Security Level Description Access Code
0 Global Access Any
1 User Access Level 1 Password Level 1 Menu
2 User Access Level 2 Password Level 2 Menu
3 Factory Only Access ---
4.2 Multiple Register Write Limitations
The Modbus Protocol requires all addresses and all data in a multiple write to be valid for any write to
occur. If an exception response occurs none of the registers are modified. Because all addresses and data
must be verified before the data is actually written, a limitation exists for multiple writes to registers
whose values are interdependent. The verification of data may fail because data to be written to one
register is invalid until data for another register is actually written. In these cases, successive single
register writes must be performed.