Asus A8R-MVP - Manual (Page 78)

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v02.58 (C)Copyright 1985-2004, American Megatrends, Inc.
BIOS SETUP UTILITY
Advanced
4.4.2 4.4.2 4.4.2 4.4.2 4.4.2 CPU Configuration CPU Configuration CPU Configuration CPU Configuration CPU Configuration
The items in this menu show the CPU-related information that the BIOS
automatically detects.
GART Error Reporting GART Error Reporting GART Error Reporting GART Error Reporting GART Error Reporting [Disabled] [Disabled] [Disabled] [Disabled] [Disabled]
Allows you to enable or disable GART error checking for testing purposes.
Configuration options: [Disabled] [Enabled]
MTRR Mapping [Continuous] MTRR Mapping [Continuous] MTRR Mapping [Continuous] MTRR Mapping [Continuous] MTRR Mapping [Continuous]
Determines the method used for programming processor MTRRs when using
more than 4 GB of system memory. Setting to [Discrete] leaves the PCI
hole below the 4 GB boundary undescribed. [Continuous] explicitly
describes the PCI hole as non-cacheable. Configuration options:
[Continuous] [Discrete]
Cool ‘n’ Quiet [ Cool ‘n’ Quiet [ Cool ‘n’ Quiet [ Cool ‘n’ Quiet [ Cool ‘n’ Quiet [Disabled Disabled Disabled Disabled Disabled]]]]]
Enables or disables the Cool ‘n’ Quiet™ technology feature.
Configuration options: [Enabled] [Disabled]
HT Link Speed [Auto] HT Link Speed [Auto] HT Link Speed [Auto] HT Link Speed [Auto] HT Link Speed [Auto]
Allows you to set the speed at which the HyperTransport link will run if the
speed is lower than or equal to the system clock and if the board is
capable. Configuration options: [Auto] [200 MHz] [400 MHz] [600 MHz]
[800 MHz] [1 GHz]
CPU Configuration
Module Version: 14.08
Physical Count: 1
Logical Count: 2
AMD Athlon(tm) 64 X2 Dual Core Processor 4600+
Revision: E6
Cache L1: 128*2 KB
Cache L2: 512*2 KB
Speed: 2400 MHz
Current FSB Multiplier: 12x
Maximum FSB Multiplier: 12x
Able to Change Freq: Yes
uCode Patch Level: 0x4D
GART Error Reporting [Disabled]
MTRR Mapping [Continuous]
Cool `n’ Quiet [Disabled]
HT Link Speed [Auto]
This option should
remain disabled for
the normal operation.
The driver developer
may enable it for
testing purpose.
Memory Configuration