Cirrus Logic CS8420 - Manual (Page 51)

DS245F4 51
CS8420
12. SOFTWARE MODE - PIN DESCRIPTION
The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pins
change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a
*, and will be described once in this section. Pins marked with a + are used upon reset to select various start-up
options, and require a pull-up or pull-down resistor.
Power Supply Connections:
VD+ - Positive Digital Power *
Positive supply for the digital section. Nominally +5.0 V.
VA+ - Positive Analog Power *
Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on
this pin will directly affect the jitter performance of the recovered clock.
DGND - Digital Ground *
Ground for the digital section. DGND should be connected to the same ground as AGND.
AGND - Analog Ground *
Ground for the analog section. AGND should be connected to the same ground as DGND.
Clock-Related Pins:
OMCK - Output Section Master Clock Input
Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso).
RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample rate (Fsi).