Cirrus Logic CS8420 - Manual (Page 29)

DS245F4 29
CS8420
8.2 Non-SRC Delay
The unit of delay depends on the frame rate (sample rate) F
s
. The AES receiver has a interface delay of two
frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay
of 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the startup uncertainty of the
logic within the part.
1. All inputs are slaves and all outputs are masters, both with respect to the outside world.
2. The inputs and outputs are synchronous to one another.
Path Delay (in units of a frame)
RX to TX 3 ± 1/128
Serial Input to TX 2 ± 1/128
RX to Serial Output 3 ± 1/128
Serial Input to Serial Output 2 ± 1/128
Table 3. Non-SRC Delay