Cirrus Logic CS8420 - Manual (Page 43)

DS245F4 43
CS8420
10.14 Receiver Channel Status (0Fh) (Read Only)
The bits in this register can be associated with either channel A or B of the received data. The
desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Regis-
ter.
AUX[3:0] The AUX3-0 bits indicate the width of the incoming auxiliary data field, as indicated by the in-
coming channel status bits, decoded according to IEC60958 and AES3.
0000 - Auxiliary data is not present
0001 - Auxiliary data is 1 bit long
0010 - Auxiliary data is 2 bits long
0011 - Auxiliary data is 3 bits long
0100 - Auxiliary data is 4 bits long
0101 - Auxiliary data is 5 bits long
0110 - Auxiliary data is 6 bits long
0111 - Auxiliary data is 7 bits long
1000 - Auxiliary data is 8 bits long
1001 - 1111 Reserved
PRO Channel status block format indicator
0 - Received channel status block is in consumer format
1 - Received channel status block is in professional format
AUDIO Audio indicator
0 - Received data is linearly coded PCM audio
1 - Received data is not linearly coded PCM audio
COPY SCMS copyright indicator
0 - Copyright asserted
1 - Copyright not asserted
ORIG SCMS generation indicator. This is decoded from the category code and the L bit.
0 - Received data is 1st generation or higher
1 - Received data is original
Note: COPY and ORIG will both be set to 1 if the incoming data is flagged as professional or if the receiver is not
in use.
7 6 5 4 3 2 1 0
AUX3 AUX2 AUX1 AUX0 PRO AUDIO COPY ORIG