Cs5550, 5 out, And out – Cirrus Logic CS5550 User Manual
Page 22: Output registers, 6 filt, Filt, Unsigned output register, 7 status register and mask register
CS5550
22
DS630F1
5.5 OUT
1
and OUT
2
Output Registers
Address:
7 (AIN1 Output Register)
8 (AIN2 Output Register)
These signed registers contain the last value of the measured results of AIN1 and AIN2. The results will be with-
in the range of -1.0
≤ AIN1,AIN2 < 1.0. The value is represented in two's complement notation, with the binary
point place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two
least significant bits, (located at the far right-side) have no meaning, and will always have a value of “0”.
5.6 FILT
1
, FILT
2
Unsigned Output Register
Address:
11 (AIN1 Filtered Output Register)
12 (AIN2 Filtered Output Register)
These unsigned registers contain the last values of FILT
1
and FILT
2
. The results are in the range of
0.0
≤ FILT
1
,FILT
2
< 1.0. The value is represented in (unsigned) binary notation, with the binary point place to
the left of the MSB. These results are updated after each computation cycle.
5.7 Status Register and Mask Register
Address:
15 (Status [Clear] Register)
Address:
26 (Mask Register)
Default** = 0x000000 (Status [Clear] Register
0x000000 (Mask Register)
The Status [Clear] Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause
the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature
the user can simply write back to the Status [Clear] Register to clear the bits that have been seen, without con-
cern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt (at the time that the
status bit is asserted), the status bit will still be set in (both of) the Status Registers so the user can poll the status.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.
DRDY
Data Ready. When running in single or continuous conversion acquisition mode, this bit will in-
dicate the end of computation cycles. When running calibrations, this bit indicates that the cal-
ibration sequence has completed, and the results have been stored in the offset or gain
OR1, OR2
AIN Output Out of Range. Set when the magnitude of the calibrated output is too large or too
MSB
LSB
-(2
0
)
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB
LSB
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
.....
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
23
22
21
20
19
18
17
16
DRDY
CRDY
OR1
OR2
15
14
13
12
11
10
9
8
FOR1
FOR2
7
6
5
4
3
2
1
0
OD2
OD1
IC