Cirrus Logic CS5550 - Manual (Page 17)

CS5550
DS630F1 17
4.1.7 Register Read/Write
The Read/Write command informs the state machine that a register access is required. During a read operation, the
addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the
data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24
th
SCLK.
W/R Write/Read control
0 = Read register
1 = Write register
RA[4:0] Register address bits (bits 1 through 5) of the read/write command.
Address RA[4-0] Abbreviation Name/Description
0 00000 Config Configuration Register
1 00001 AIN1 DCoff AIN1 Offset Register
2 00010 AIN1 gn AIN1 Gain Register
3 00011 AIN2
DCoff
AIN2 Offset Register
2 00100 AIN2 gn AIN2 Gain Register
5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)).
6 00110 Res Reserved †
7 00111 OUT
1
AIN1 Output Register
8 01000 OUT
2
AIN2 Output Register
9 01001 Res Reserved †
10 01010 Res Reserved †
11 01011 FILT
1
Computed Filtered value for AIN1
12 01100 FILT
2
Computed Filtered value for AIN2
13 01101 Res Reserved †
14 01110 Res Reserved †
15 01111 Status Status Register
16 10000 Res Reserved
17 10001 Res Reserved
18 10010 Res Reserved †
19 10011 Res Reserved
20 10100 Res Reserved †
21 10101 Res Reserved †
22 10110 Res Reserved †
23 10111 Res Reserved †
24 11000 Res Reserved †
25 11001 Res Reserved †
26 11010 Mask Mask Register
27 11011 Res Reserved †
28 11100 Ctrl Control Register
29 11101 Res Reserved †
30 11110 Res Reserved †
31 11111 Res Reserved †
† These registers are for internal use only. For proper device operation, the user must not attempt to write
to these registers.
B7 B6 B5 B4 B3 B2 B1 B0
0 W/R RA4 RA3 RA2 RA1 RA0 0