Cirrus Logic AN118 - Manual (Page 6)

AN118
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data is then transferred to the ADC, and SDO is
polled until the conversion is ready. A byte of zeros
is then transmitted to the ADC to begin the data
transfer, and the data word is received. The data
word is then sent to the PC, and the process is re-
peated until the sample size has been reached. Once
enough samples have been collected and trans-
ferred to the PC, a command byte consisting of all
ones is sent to the ADC to instruct it to stop con-
verting data, and the final conversion word is re-
ceived from the ADC and discarded.
Variable Number of Offset or Gain Calibrations -
When more than one offset or gain calibration is re-
quested, the software obtains a sample index, the
type of calibration (self or system), and which Set-
up is being used to calibrate from the PC.
Decode_sample_index is called to determine the
actual number of calibrations to be performed, and
then the calibration type is sent to the ADC. SDO is
polled until the calibration is completed, and then
the calibration register is sent. The calibrated regis-
ter is returned by the ADC, and sent to the PC. This
process continues until the number of calibrations
requested have been performed.
Serial Port Initialization - This routine re-initializes
the serial port on the ADC if it is requested. To ac-
complish this, the SDI pin is set to a logic high lev-
el, and SCLK is pulsed 255 times. SDI is then
brought low and a single SCLK pulse is sent. This
initialization routine is the same as what is done
within the start-up initialize command, but is limit-
ed to the serial port on the ADC.
Reset Converter Via RS and RV Bits - This routine
resets the ADC, and returns all of its internal regis-
ters to their initial states. The command 0x03 fol-
lowed by 0x800000(HEX) is sent to the ADC,
which sets the RS (Reset) bit and nothing else.
Then the 0x0B(HEX) register is read, and the low
byte is masked for the RV (Reset Valid) bit. If a
valid reset has occurred, the RS bit is cleared. If no
valid reset has occurred, the routine continues to
cycle and poll the RV bit until the reset is success-
ful.
Read Output Latch Pins - The ADC’s output latch
pins (A0 and A1) are connected to pins P1.4 and
P1.5, respectively, on the 80C51. If the PC requests
the status of these pins, they are read from the prop-
er pins and transmitted to the PC.
Arbitrary Read - This routine is used to read any
number of bytes from the ADC and return them to
the PC. The number of bytes requested is obtained
from the PC, and then bytes are successively read
from the ADC and transmitted to the PC until that
number has been reached.
Arbitrary Write - This routine asks for one byte
from the PC, and transfers it to the ADC.
If none of these conditions are met, the software
does nothing but return to the main routine.
3.6 Sample Index
When the PC requests an entire sample set, the mi-
crocontroller code assumes that it will be sending a
sample index. This number, 0-10, is passed to the
decode_sample_index routine to select one of the
ten sample set size options. The sample set sizes are
based on the FFT algorithms in the PC evaluation
board software, which require a sample set size of
samples, and the software’s internal limitation
of between 16 and 8192 samples. A single sample
option is also included, and if none of these are se-
lected, the sample size defaults to zero.
3.7 Test Modes
There are a seven self-test modes built in the con-
troller software, contained in the routine test_mode.
These tests allow the user to troubleshoot certain
problems that may be occurring with the evaluation
board and its software. The test modes are entered
by setting the DIP switches to a value greater than
zero and resetting the board. This instructs the main
routine to skip over the normal operation loop and
go straight into test mode. To exit any of these rou-
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