Cirrus Logic CRD5381 - Manual (Page 5)

DS563RD1 5
CRD5381
1.2 CS8421 Output and the Interface Clock Domain
1.2.1 CS8421 Output System Clocking
The CS8421 serial output is configured as a system clock slave. The advantages are:
• Output sample rate is dependent on the frequency of the incoming word clock (OLRCK), set by the user.
• Outputs of multiple CS8421 devices are synchronous.
• Multiple devices can be configured in a Time Division Multiplexed (TDM) multi-channel interface format.
As mentioned in “CS8421 Input Operational Mode” on page 4, the input of the CS8421 is configured as a
master, with the master clock frequency = 128*Fsi (or ILRCK). To accommodate this serial input mode, and
to set the serial output to slave, the MS_SEL pin is connected to +3.3 V.
1.2.2 Serial Audio Output Port Options and Selection of Data Resolution and Dither
The CS8421 provides multiple options for the serial audio output port. These options include:
• Output Data Format of Left-Justified, Right-Justified, I²S or TDM
• Audio output data resolution of the SRC can be set to 16, 20, 24, or 32-bits. Dithering is applied and is
automatically scaled to the selected output word length. This dither is not correlated between left and
right channels.
Output word-length and serial data format are selected with either a pull-up or pull down resistor connected
to the SAOF pin of the CS8421. Please refer to Table 3 in the CS8421 data sheet for details [3].
The serial audio output of the CRD5381 is configured to operate in either dual 24-bit Left-Justified formats
or a 4-channel 24-bit TDM output.
1.2.3 Clocking
In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneously
satisfy the requirements of LRCK for both the input and output as follows:
• If the input is set to master, Fsi ≤ XTI/128 and Fso ≤ XTI/130.
• If the output is set to master, Fso ≤ XTI/128 and Fsi ≤ XTI/130.
• If both input and output are set to slave, XTI ≥ 130*[maximum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso <
3750.
In the example application in this data sheet, the input serial port is set to master, and generates serial
clocks for a sampling rate of XTI/128. The output serial port is set as slave, and can receive a left-right clock
that is
≤ XTI/130. The serial bit-clock frequency is always 64*left-right clock.
1.2.4 SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this in-
formation to set up various parameters inside the SRC block. The SRC takes approximately 4200/Fso
(8.75 ms at Fso of 48 kHz) to make this calculation.
The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK
pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to un-mute its output.