Cirrus Logic CRD5381 - Manual (Page 3)

DS563RD1 3
CRD5381
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ................................................................................................................ 4
1.1 Sample Clock Domain ....................................................................................................... 4
1.1.1 CS8421 Input Operational Mode .......................................................................... 4
1.1.2 CS5381 Operational Mode ................................................................................... 4
1.1.3 Master Clock Frequency Generation .................................................................... 4
1.1.4 Maximum Sample Rate ......................................................................................... 4
1.1.5 Synchronization of Multiple Sections .................................................................... 4
1.2 CS8421 Output and the Interface Clock Domain .............................................................. 5
1.2.1 CS8421 Output System Clocking ......................................................................... 5
1.2.2 Serial Audio Output Port Options and Selection of Data Resolution and Dither ... 5
1.2.3 Clocking ................................................................................................................ 5
1.2.4 SRC Locking and Varispeed ................................................................................. 5
1.2.5 Latency or Group Delay ........................................................................................ 6
1.2.6 Phase Matching Between Multiple Sections ......................................................... 6
1.3 Filter Response ................................................................................................................. 7
2. OPERATION .............................................................................................................................. 9
2.1 Sample Rate ...................................................................................................................... 9
2.2 Audio Data Output Format Selection ................................................................................. 9
2.3 System Clocking and Data I/O .......................................................................................... 9
2.4 System Status Indicators ................................................................................................. 10
2.5 System Reset .................................................................................................................. 10
2.6 Analog Inputs ................................................................................................................... 11
2.7 Power .............................................................................................................................. 11
2.8 Grounding and Power Supply Decoupling ....................................................................... 11
3. BLOCK DIAGRAM .................................................................................................................. 12
4. SCHEMATICS ......................................................................................................................... 13
5. LAYOUT .................................................................................................................................. 19
6. REFERENCES ......................................................................................................................... 24
7. REVISION HISTORY ............................................................................................................... 24
LIST OF FIGURES
Figure 1. Transitional Band, 48 kHz Out ......................................................................................... 7
Figure 2. Transitional Band, 96 kHz Out ......................................................................................... 8
Figure 3. Transitional Band, 192 kHz Out ....................................................................................... 8
Figure 4. Left-Justified Serial Audio Interface ................................................................................. 9
Figure 5. TDM Audio Interface ........................................................................................................ 9
Figure 6. Clock and Data Header Connections, J4....................................................................... 10
Figure 7. Status Indicator and Reset Header, J16 ........................................................................ 11
Figure 8. Block Diagram................................................................................................................ 12
Figure 9. Analog Inputs 1 & 2........................................................................................................ 13
Figure 10. Analog Inputs 3 & 4...................................................................................................... 14
Figure 11. CS5381 & CS8421 Pair A............................................................................................ 15
Figure 12. CS5381 & CS8421 Pair B............................................................................................ 16
Figure 13. I/O Header and Miscellaneous..................................................................................... 17
Figure 14. Power........................................................................................................................... 18
Figure 15. Silk Screen................................................................................................................... 19
Figure 16. Top Layer..................................................................................................................... 20
Figure 17. Bottom Layer................................................................................................................ 21
Figure 18. Power Plane................................................................................................................. 22
Figure 19. Ground Plane............................................................................................................... 23