Cirrus Logic CDB5331A - Manual (Page 2)

CDB5330A/31A System Overview
The CDB5330A/31A evaluation board is an ex-
c el l en t mean s of qu ick ly eval uat ing th e
CS5330A/31A. The CS8402A digital audio in-
terface transmitter provides an easy interface to
digital audio signal processors, including the ma-
jority of digital audio test equipment. The
evaluation board has been designed to accept an
analog input, and provide a digital output that is
either optical or coax. The evaluation board also
allows the user to supply clocks and data
through a 10-pin header for system development.
The CDB5330A/31A schematic has been parti-
tioned into 5 schematics shown in Figures 2
through 6. Each partitioned schematic is repre-
sented in the system diagram shown in Figure 1.
Notice that the the system diagram also includes
the interconnections between the partitioned
schematics.
CS5330A/31A Analog to Digital Converter
A description of the CS5330A/31A is included
in the CS5330A/31A data sheet.
CS8402A Digital Audio Interface
Figure 4 shows the CS8402A circuitry which
implements AES/EBU, S/PDIF and EIAJ CP-
340 digital audio interface standards. The
CS8402A circuit is hardware configured for con-
sumer mode. SW2 provides 8 DIP switches to
select various modes and bits for the CS8402A,
Tables 4-5. See the CS8401A/CS8402A data
sheet for detailed information on the operation of
the CS8402A and the digital audio standards.
The operation of the CS8402A and a discussion
of the digital audio interface are included in the
1994 Crystal Semiconductor Audio Data Book.
CS8402A Data Format
The CS8402A data format can be set with jump-
ers M0, M1, and M2. These formats are shown
in the CS8402A datasheet found in the 1994
Crystal Semiconductor Audio Data Book. The
format selected must be compatible with the cor-
responding data format of the CS5330A/31A
shown in Figures 2 and 3 of the CS5330A/31A
datasheet. The default settings for M0-M2 on the
evaluation board are given in Tables 2 and 3.
The compatible data formats for the CS8402A
and CS5330A/31A are:
CS8402A format 1;CS5330A
CS8402A format 4;CS5331A
Analog input buffer
The recommended input filter required for the
CS5330A/31A has been combined with a unity
gain input buffer (see Figure 2). The analog in-
put filter uses a Motorola MC33202 single
supply, dual op-amp.
Power Supply Circuitry
Power is supplied to the evaluation board by two
binding posts (GND, +5V), Figure 6. The +5V
input supplies power to the +5 Volt digital cir-
cuitry (VD+), and the +5V analog circuitry
(VA+). The analog supply is derived from the
+5V binding post through a ferrite bead.
Input/Output for Clocks and Data
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
CLOCK I/O header, HDR2. This header allows
the evaluation board to accept externally gener-
ated clocks. The schematic for the clock/data I/O
is shown in Figure 5. The 74HC243 transceiver
functions as an I/O buffer where the MAS-
T E R / SL AV E j ump e r d e te rmi n es if t he
transceiver operates as a transmitter or receiver.
CDB5330A / CDB5331A
18 DS138DB2