Cirrus Logic CS4396 User Manual
Advance product information, Features, Description
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4396
24-Bit, 192 kHz D/A Converter for Digital Audio
Features
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24 Bit Conversion
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Up to 192 kHz Sample Rates
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120 dB Dynamic Range
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-100 dB THD+N
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Advanced Dynamic-Element Matching
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Low Clock Jitter Sensitivity
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Digital De-emphasis for 32 kHz, 44.1 kHz and
48 kHz
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External Reference Input
Description
The CS4396 is a complete high performance 24-bit
48/96/192 kHz stereo digital-to-analog conversion sys-
tem. The device includes a digital interpolation filter
followed by a oversampled multi-bit delta-sigma modula-
tor which drives dynamic-element-matching (DEM)
selection logic. The output from the DEM block controls
the input to a multi-element switched capacitor DAC/low-
pass filter, with fully-differential outputs. This multi-bit ar-
chitecture features significantly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced DEM guarantees low noise and distortion at
all signal levels.
ORDERING INFORMATION
CS4396-KS
-10° to 70° C 28-pin Plastic SOIC
CDB4397
Evaluation Board
I
SCLK
MCLK
M4
LRCK
SDATA
AOUTL+
AOUTR+
SERIAL INTERFACE
AND FORMAT SELECT
INTERPOLATION
SOFT MUTE
∆Σ
MODULATOR
DYNAMIC
DE-EMPHASIS
SWITCHED
AOUTL-
AOUTR-
FILT+
FILTER
INTERPOLATION
FILTER
FILTER
MULTI-BIT
∆Σ
MODULATOR
MULTI-BIT
ELEMENT
MATCHING
LOGIC
DYNAMIC
ELEMENT
MATCHING
LOGIC
CAPACITOR-DAC
AND FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
VREF
CMOUT
FILT-
VOLTAGE REFERENCE
HARDWARE MODE CONTROL
CLOCK
DIVIDER
(CONTROL PORT)
(AD0/CS)
M3
M2
(AD1/CDIN) (SCL/CCLK)
M1
M0
(SDA/CDOUT)
RESET
MUTEC MUTE
JUL ‘99
DS288PP1
Document Outline
- CS4396
- Features
- Description
- Table of Contents
- Table of Figures
- 1.0 Characteristics/Specifications
- 2.0 Typical Connection Diagram
- 3.0 Register Description
- 4.0 PIN DESCRIPTION
- Pin Description Drawing
- Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies
- Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
- Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
- Reset - RST
- Digital Ground - DGND
- Digital Power - VD
- Master Clock - MCLK
- Serial Clock - SCLK
- Left/Right Clock - LRCK
- Serial Audio Data - SDATA
- Soft Mute - MUTE
- Control Port / Hardware Mode Select - C/H
- Mute Control - MUTEC
- Analog Ground - AGND
- Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- , AOUTL+
- Analog Power - VA
- Common Mode Voltage - CMOUT
- Reference Ground - FILT-
- Reference Filter - FILT+
- Voltage Reference Input- VREF
- HARDWARE MODE
- CONTROL PORT MODE
- 5.0 APPLICATIONS
- 6.0 Control Port Interface
- 6.1 SPI Mode
- 6.2 I2C Mode
- Memory Address Pointer (MAP)
- Figure 5. Control Port Timing, SPI mode
- Figure 6. Control Port Timing, I2C Mode
- Table 7. Single Speed (16 to 50kHz) Digital Interface Format Options
- Table 8. Single Speed (16 to 50kHz) De-Emphasis Options
- Table 9. Double Speed (50 to 100 kHz) Sample Rate Mode Options
- Table 10. Quad (100 to 200 kHz) Sample Rate Mode Options
- Figure 7. Single-speed Transition Band
- Figure 8. Single-speed Stopband Rejection
- Figure 9. Single-speed Transition Band
- Figure 10. Single-speed Frequency Response
- Figure 11. Double-speed Stopband
- Figure 12. Double-speed Transition Band
- Figure 13. Double-speed Transition Band
- Figure 14. Double-speed Frequency Response
- Figure 15. Quad-speed Stopband Rejection
- Figure 16. Quad-speed Transition Band
- Figure 17. Quad-speed Transition Band
- Figure 18. Quad-speed Frequency Response
- Figure 19. De-Emphasis Curve
- Figure 20. Format 0, Left Justified
- Figure 21. Format 1, I2S
- Figure 22. Format 2, Right Justified, 16-Bit Data
- Figure 23. Format 3, Right Justified, 24-Bit Data
- Memory Address Pointer (MAP)
- 7.0 PARAMETER DEFINITIONS
- 8.0 REFERENCES
- 9.0 PACKAGE DIMENSIONS