Cirrus Logic CS4364 - Manual (Page 42)

42 DS619F1
CS4364
6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)
These six registers provide individual volume and mute control for each of the six channels.
The values for “xx” in the bit fields above are as follows:
Register address 0Bh - xx = A1
Register address 0Ch - xx = B1
Register address 0Eh - xx = A2
Register address 0Fh - xx = B2
Register address 11h - xx = A3
Register address 12h - xx = B3
6.11.1 Digital Volume Control (xx_VOL7:0)
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in
Table 10 . The volume changes are imple-
mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that
the values in the volume setting column in
Table 10 are approximate. The actual attenuation is determined
by taking the decimal value of the volume register and multiplying by 6.02/12.
6.12 PCM Clock Mode (Address 16h)
6.12.1 Master Clock Divide by 2 Enable (MCLKDIV)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
7 6 5 4 3 2 1 0
xx_VOL7 xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0
0 0 0 0 0 0 0 0
Binary Code Decimal Value Volume Setting
00000000 0 0 dB
00000001 1 -0.5 dB
00000110 6 -3.0 dB
11111111 255 -127.5 dB
Table 10. Example Digital Volume Settings
7 6 5 4 3 2 1 0
Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0