Cirrus Logic CS4364 - Manual (Page 3)

DS619F1 3
CS4364
6.3 PCM Control (Address 03h) .......................................................................................................... 34
6.3.1 Digital Interface Format (DIF)............................................................................................... 34
6.3.2 Functional Mode (FM) .......................................................................................................... 35
6.4 DSD Control (Address 04h) ........................................................................................................... 35
6.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................. 35
6.4.2 Direct DSD Conversion (DIR_DSD) ..................................................................................... 36
6.4.3 Static DSD Detect (STATIC_DSD) ...................................................................................... 36
6.4.4 Invalid DSD Detect (INVALID_DSD).................................................................................... 36
6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE).................................................... 36
6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ........................................................ 36
6.5 Filter Control (Address 05h) .......................................................................................................... 37
6.5.1 Interpolation Filter Select (FILT_SEL).................................................................................. 37
6.6 Invert Control (Address 06h) ......................................................................................................... 37
6.6.1 Invert Signal Polarity (INV_xx) ............................................................................................. 37
6.7 Group Control (Address 07h) ........................................................................................................ 37
6.7.1 Mute Pin Control (MUTEC1, MUTEC0) ............................................................................... 37
6.7.2 Channel A Volume = Channel B Volume (Px_A=B)............................................................. 37
6.7.3 Single Volume Control (SNGLVOL) ..................................................................................... 38
6.8 Ramp and Mute (Address 08h) ..................................................................................................... 38
6.8.1 Soft Ramp and Zero Cross Control (SZC) ........................................................................... 38
6.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ..................................................................... 39
6.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) ................................................... 39
6.8.4 PCM Auto-Mute (PAMUTE) ................................................................................................. 39
6.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................. 39
6.8.6 MUTE Polarity and DETECT (MUTEP1:0)........................................................................... 40
6.9 Mute Control (Address 09h) .......................................................................................................... 40
6.9.1 Mute (MUTE_xx) .................................................................................................................. 40
6.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) ............................................................................. 40
6.10.1 De-Emphasis Control (PX_DEM1:0) .................................................................................. 40
6.10.2 ATAPI Channel Mixing and Muting (ATAPI) ...................................................................... 41
6.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h)........................................................... 42
6.11.1 Digital Volume Control (xx_VOL7:0) .................................................................................. 42
6.12 PCM Clock Mode (Address 16h) ................................................................................................. 42
6.12.1 Master Clock Divide by 2 Enable (MCLKDIV) .................................................................... 42
7. FILTER RESPONSE PLOTS ............................................................................................................... 43
8. REFERENCES...................................................................................................................................... 47
9. PARAMETER DEFINITIONS................................................................................................................ 47
10. PACKAGE DIMENSIONS .................................................................................................................. 48
11. ORDERING INFORMATION .............................................................................................................. 49
12. REVISION HISTORY ......................................................................................................................... 50