Cirrus Logic CS43122 User Manual

Page 17

CS43122

MUTE

Soft Mute

(Input) - The analog outputs will ramp to a muted state when enabled.

The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles
in Operational Mode 1 and 4608 cycles in Operational Mode 2 . The bias voltage
on the outputs will be retained and MUTEC will go active at the completion of the
ramp period.
The analog outputs will ramp to a normal state when this function transitions from
the enabled to disabled state. The ramp requires 1152 left/right clock cycles in
Operational Mode 0, 2304 cycles in Operational Mode 1 and 4608 cycles in Oper-
ational Mode 2 . The MUTEC will release immediately on setting MUTE = 1.
The converter analog outputs will mute when enabled. The bias voltage on the
outputs will be retained and MUTEC will go active during the mute period

C/H

Control Port / Hardware Mode Select

(Input) - Determines if the device will oper-

ate in either the Hardware Mode or Control Port Mode.

MUTEC

Mute Control

(Output) - The Mute Control pin goes low during power-up initializa-

tion, reset, muting, master clock to left/right clock frequency ratio is incorrect or
power-down. This pin is intended to be used as a control for an external mute circuit
to prevent the clicks and pops that can occur in any single supply system. Use of
Mute Control is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops.

AGND

18, 21

Analog Ground

(Inputs) - Analog ground reference.

AOUTR- , AOUTR+
AOUTL- , AOUTL+

19, 20,

23, 24

Differential Analog Outputs

(Outputs) - The full scale differential analog output

level is specified in the Analog Characteristics specifications table.

Analog Power

(Input) - Power for the analog and reference circuits. Typically

5.5 VDC.

CMOUT

Common Mode Voltage

(Output) - Filter connection for internal bias voltage, typ-

ically 50% of VREF. Capacitors must be connected from CMOUT to analog
ground, as shown in the Typical Connection Diagram. CMOUT has a typical
source impedence of 25 k

Ω

and any current drawn from this pin will alter device

performance.

FILT-

Reference Ground

(Input) - Ground reference for the internal sampling circuits.

Must be connected to analog ground.

FILT+

Reference Filter

(Output) - Positive reference for internal sampling circuits. Exter-

nal capacitors are required from FILT+ to analog ground, as shown in the Typical
Connection Diagram. The recommended values will typically provide 60 dB of
PSRR at 1 kHz and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply
external current.

VREF

Voltage Reference Input

(Input) - Analog voltage reference. Typically 5.5 VDC.

M0, M1, M2, M3, M4
(Hardware Mode)

2, 3, 4,

5,14

Mode Select

(Inputs) - The Mode Select pins determine the operational mode of

the device as detailed in Tables 4-7. The options include;
Selection of the Digital Interface Format which determines the required relation-
ship between the Left/Right clock, serial clock and serial data as detailed in Fig-
ures 20-23Selection of the standard 15

s/50

s digital de-emphasis filter

response, Figure 28, which requires reconfiguration of the digital filter to maintain
the proper filter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input sample rates.

AD0 / CS
(Control Port Mode)

Address Bit 0 / Chip Select

(Input) - In 2 wire mode, AD0 is a chip address bit.

CS is used to enable the control port interface in SPI mode. The device will enter
the SPI mode at anytime a high to low transition is detected on this pin. Once the
device has entered the SPI mode, it will remain until either the part is reset or
undergoes a power-down cycle.